The present invention relates generally to power metaloxide-semiconductor field-effect transistors (MOSFET's) manufactured by double diffusion techniques and, more particularly, to methods of manufacturing such transistors with a minimum of masking steps, methods for forming ohmic shorts between the source and base layers during the manufacture of such transistors, and transistors so manufactured.
Known power MOSFET's generally comprise a multiplicity of individual unit cells (numbering in the thousands) formed on a single silicon semiconductor wafer with each device being of the order of 300 mils (0.3 in.) square in size and all cells in each device being electrically connected in parallel. Each cell is typically between 5 and 50 microns in width. As is described more fully hereinbelow, one particular known process for manufacturing power MOSFET's is a double diffusion technique which begins with a common drain region of, for example, N type semiconductor material. Specifically, within the drain region a base region is formed by means of a first diffusion, and then a source region is formed entirely within the base region by means of a second diffusion. If the drain region is N type, then the first diffusion is done with acceptor impurities to produce a P type base region, and the second diffusion is done with donor impurities to produce an N.sup.+ type source region.
In a power MOSFET structure, the source, base and drain regions correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. As is known, if this parasitic bipolar transistor is allowed to turn on during operation of the power MOSFET, the blocking voltage and the dV/dt rating of the power MOSFET are substantially degraded. Accordingly, in order to prevent the turn on of the parasitic bipolar transistor during operation of the power MOSFET, the layers comprising the source and base regions are normally shorted together by means of an ohmic connection.
Known power MOSFET designs in manufacture require up to six masking steps, some of which must be aligned to each other with high accuracy to produce working devices. In particular, to form the source-base short, between the first and second diffusion steps a diffusion barrier is applied by means of selective masking over a portion of the base diffusion surface area to prevent the subsequent source diffusion from entering the base diffusion in this area. Thereafter, metallization is applied for the source electrode, and a portion of the source metallization also makes ohmic contact with the previously masked area of the base region.
In this known technique for manufacturing power MOSFET's, not only must the masking pattern to form the source-base shorts be precisely aligned in a special manufacturing step, but the short occupies a significant fraction of the area of each MOSFET unit cell without contributing to its conductivity during the ON state.